Programmable integrated circuits such as field programmable gate arrays (FPGAs) and complex programmable logic devices (CPLDs) are examples of integrated circuit devices that have an array of programmable logic blocks surrounded by peripheral input/output blocks. Also located within the array are signal routing resources that are programmable. Programmable logic blocks are often referred to as configurable logic blocks (CLBs). CLBs may be configured to implement specific logic functions selected from a macro cell library. Many manufacturers of ASICs, FPGAs or CPLDs have developed extensive libraries of logic functions that may be implemented in the CLBs. As is well understood in the art, FPGAs and CPLDs may be configured to rapidly perform desired logic functions to shorten the design and fabrication time schedule of a custom integrated circuit device.
Typically, each CLB has a plurality of input ports (for example, 15 inputs) which may include signals, clock and control inputs, and a plurality of output ports (for example, 5 outputs). Using the programmable routing resources discussed above, each CLB input and output port (e.g., "input" and "output") can be programmably connected by interconnect segments to other selected CLB outputs and its input or to the input/output blocks. In this manner, circuit designers can implement complex logic functions on the integrated circuit device. These interconnect segments are laid out in areas of the device between the CLBs and between the CLBs and the input/output blocks reserved for such interconnections. The segments are typically routed in either a horizontal or vertical direction with, by way of example, the horizontal metal segments routed in a layer of metal either above or below the vertical metal segments.
As manufacturing techniques improve, the size of the CLBs decreases and thereby the number of CLBs that can be placed within a programmable logic device increases. As the number of CLBs that can be provided within an array increases, the complexity of logic functions that can programmed onto the integrated circuit device also increases. However, as the number of CLBs increases, signal routing between CLBs and input/output blocks becomes a major problem for circuit designers. As is well known in the art, routing the interconnections between large numbers of CLBs is a very difficult task that: (1) requires sophisticated placement and routing application software; and (2) demands large amounts of routing resources, (e.g., routing time is a function of the routing resources).
In prior art programmable logic devices, the locations of the signal routing resources are predefined. In effect, unlike the CLBS, the signal routing resources of the prior art are not modular, e.g., they are not provided in discrete "cells" that can be placed within the array. Therefore, a signal routing resource allocation or design that is operable for an N.times.N array can supply extremely insufficient amount of interconnects for a larger array (e.g., 2N.times.2N).
Therefore, a significant limitation on the complexity of logic functions that can be implemented on the integrated circuit device is attributed to a lack of sufficient routing resources for interconnecting CLBs within a programmable logic array. In view of this limitation, it is a common practice to fully utilize all routing resources within a programmable logic array long before all of the available CLBs can be utilized. As will be appreciated by one skilled in the art, routing congestion usually occurs worst in the middle of the circuit or in other known areas of the circuit. CLB "under-utilization" is expensive because the price of integrated circuit devices is highly dependent on the physical dimension of the device and full CLB utilization is desired.
One method to increase CLB utilization is to manually lay-out a portion of the routing resources ("interconnects"). For instance, this method would provide for manually redesigning the predefined routing resource design for a programmable logic device based on its array size. However, manual lay-out is a time consuming and expensive task that is prone to mistakes. Further, it is difficult and time consuming to run design verification and simulation software on circuits having at least a portion of the interconnections manually redone thereby increasing the possibility that design errors will not be detected until after release of the circuit. Lastly, since the number of array sizes is only limited by semiconductor fabrication equipment, this method can require a new interconnect design for each array size.
One method to increase signal routing resources within a programmable array is to increase the resource allotment within the macro cell defining the CLB. However, doing so can require modification of the macro cell library of logic functions when the macro cells include the interconnect segments. Modification of the macro cell library is a time consuming effort and, once modified, each macro cell must be resimulated and proper operation verified, which is an expensive and time consuming task. Also, modifying each macro cell can be unnecessary because routing congestion usually occurs in particular selected targeted areas, as indicated above. If the above is done, then the die size increases as well as the cost thereof and, in addition, many routing resources may be left unused.
Accordingly, it would be desirable to provide a signal routing design that provides a more modular mechanism for providing signal routing resources to a programmable logic array. Further, it would be desirable to provide, in a system as above, additional routing channels in selected areas of the programmable arrays where signal congestion typically is encountered. Finally, it would be desirable to provide the above within a circuit design that does not require modification of the CLB macro cell design so that existing libraries can be used to provide new, high density, device families that have significant numbers of CLBs on the device.